VLSI PROJECT LIST (VHDL/Verilog) |
Project list  |
| S.No. |
PROJECT TITLES |
VHDL |
Abstracts |
| 188 |
An Efficient Implementation of Floating Point Multiplier |
VHDL |
Download |
| 189 |
An Efficient Architecture for 3-D Discrete Wavelet Transform. (Verilog) |
Verilog |
Download |
| 190 |
A Spurious-Power Suppression Technique for Multimedia/DSP Applications(Verilog) |
Verilog |
Download |
| 191 |
Design of On-Chip Bus with OCP Interface. (VHDL) |
VHDL |
Download |
| 192 |
DDR3 based lookup circuit for high-performance network processing. (Verilog) |
Verilog |
Download |
| 193 |
Multiplication Acceleration Through Twin Precision(VHDL) |
VHDL |
Download |
| 194 |
Implementation of FFT/IFFT Blocks for OFDM(VHDL) |
VHDL |
Download |
| 195 |
A Very fast and low power Carry select adder Circuit |
Verilog |
Download |
| 196 |
Implementation of UART Serial communication module based on VHDL |
VHDL |
Download |
| 197 |
RCEAT for Radio Frequency Identification (RFID) UHF Tag(Verilog) |
Verilog |
Download |
| 198 |
DA-based DCT core with an error-compensated adder-tree (ECAT)
VHDL |
VHDL |
Download |
| 199 |
Low power ALU Design By Ancient Mathematics |
VHDL |
Download |
| 200 |
Efficient FPGA implementation of convolution |
VHDL |
Download |
| 201 |
Implementation of Carry Tree Adders using Verilog |
Verilog |
Download |
| 202 |
Implementation of Self-motivated Arbitration Scheme for the multi-layer AHB-Bus Matrix(Verilog) |
Verilog |
Download |
| 203 |
Self-Immunity Technique to Improve Register File Integrity against Soft Errors (Verilog) |
Verilog |
Download |
| 204 |
Implementation Of Hamming Code Using Verilog HDL |
Verilog |
Download |
| 205 |
Design of Parallel Multiplier Based on Radix-2 Modified Booth Algorithm (Verilog) |
Verilog |
Download |
| 206 |
Design and Implementation of Adaptive Viterbi Decoder (Verilog) |
Verilog |
Download |
| 207 |
High Performance Complex Number Multiplier Using Booth-Wallace Algorithm |
VHDL |
Download |
| 208 |
Design Of JPEG Image Compression Standard(Verilog) |
Verilog |
Download |
| 209 |
Design of an Bus Bridge between OCP and AHB Protocol (VHDL) |
VHDL |
Download |
| 210 |
Design of 16 Point Radix-4 FFT (Fast Fourier Transform) Algorithm(Verilog) |
Verilog |
Download |
| 211 |
Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block(VHDL) |
VHDL |
Download |
| 212 |
Design of 32bit RISC PROCESSOR(VHDL) |
VHDL |
Download |
| 213 |
VMFU Design Using Spurious Power Suppression Technique |
Verilog |
Download |
| 214 |
Design of 16-bit QPSK |
Verilog |
Download |
| 215 |
Design of 64-bit QAM |
Verilog |
Download |
| 216 |
High Speed VLSI architecture for General Linear Feedback Shift Registers |
Verilog |
Download |
| 217 |
Implementation of High speed DDRSDRAM Controller |
VHDL |
Download |
| 218 |
Implementation of Guessing Game using VHDL |
VHDL |
Download |
| 219 |
Implementation of Traffic light controller using VHDL |
VHDL |
Download |
| 220 |
Implementation of DWT using(5,3) Lifting Scheme |
Verilog |
Download |
| 221 |
Design of Radix-2 Butterfly Processor to Prevent Overflow in the Arithmetic |
VHDL |
Download |
| 222 |
Design and Implementation of Systollic array Architecture for DWT |
Verilog |
Download |
