MODULE - 1: Introduction to VLSI
MODULE - 2: Advanced Digital Design
MODULE - 3: Verilog HDL – RTL Coding and Synthesis
MODULE - 4: FPGA Implementation
MODULE - 5: Case Study – RTL Coding, Synthesis and FPGA    Implementation

Program Details
Program Name   : Training in VLSI Design–Front End
Duration              : 10 Weeks           

EDA Partners & Tools

• Mentor Graphics
• MODELSIM – HDL Simulation
• Xilinx
• Xilinx ISE (Integrated Software Environment) – HDL Synthesis
• ChipScope Pro – FPGA Programming

Detailed Course Contents
MODULE - 1: Introduction to VLSI

• Scope of VLSI
• Today’s VLSI Design
• Introduction to CMOS Technology
• VLSI Design Flow
• ASIC Vs FPGA
• Design Methodologies
• Introduction to Verification Methodologies

MODULE - 2: Advanced Digital Design

• Introduction to Digital Electronics
• Universal Logic Elements
• Combinational Circuits - Design and Analysis 

• Arithmetic Circuits
• Data processing Circuits

• Sequential Circuits - Design and Analysis

• Latches and Flip flops
• Shift Registers and Counters
• Memories – ROM and RAM

• Finite State Machine

MODULE – 3: Verilog HDL – RTL Coding and Synthesis
Introduction to Verilog HDL

• Scope and Applications of Verilog HDL
• Verilog HDL language concepts
• Verilog language basics and constructs
• Abstraction levels

Data Types

• Type concept
• Nets and registers
• Constants
• Arrays

Verilog Operators

• Logical operators
• Bitwise and Reduction operators
• Concatenation and Conditional
• Relational and arithmetic
• Shift and Equality operators
• Operators precedence

Styles of Modeling

• Structural Modeling
• Data Flow Modeling

• Continuous Assignments

• Behavioral Modeling

• Procedural Assignments
• Blocking and Non-Blocking assignments
• Conditional Statements

Assignments

• Timing References
• Execution Branching
• Tasks and Functions

Finite State Machine

• Basic FSM structure
• Moore Vs Mealy
• Common FSM coding styles
• State Encoding Techniques

Advanced Verilog for Verification

• Test Bench Development
• System Tasks
• Internal variable monitoring
• Compiler directives

• Constants
• Macros
• Include Files
• Comments

• File input and output Functions
• Introduction to System Verilog

Synthesis Coding Style

• HDL Synthesis
• Unwanted latches
• Operator synthesis
• RTL Synthesis Guidelines

MODULE - 4: FPGA Implementation

• Introduction to PLA and PLD
• FPGA Vs CPLD
• Xilinx CPLD Structure
• FPGA Architectures

• Concept of CLB and FPGA Structure
• Reconfigurability
• Distributed RAM
• Digital Clock Managers
• Macros

• Xilinx FPGA Implementation Flow

• FPGA programming
• UCF constraints
• Translate, Map, Floorplan, Place and Route
• Post map and Post P&R simulation
• Reading and analyzing reports – Post Synthesis, Post Map simulation, Post P&R simulation
• Generating BITMAP File and Configuring FPGAs

• Xilinx FPGA Implementation Flow - DEMO

MODULE – 5: Case Study – RTL Coding, Synthesis and FPGA    Implementation

• Project Specification Analysis
• Understanding the architecture
• Module level implementation and verification
• Building the top level module
• Building Test Bench for the top level module
• Implementing the design onto the FPGA board