Download Project List |
Sno
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Projects List
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IEEE Year
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Abstract
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Base Paper
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Front End Design(VHDL/Verilog HDL) |
1. |
A Low-Power Parallel Architecture for
Linear Feedback Shift Registers
|
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2. |
FSM based High Speed VLSI Architecture for DBUTVF Algorithm |
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3. |
Machine Learning based Power Efficient Approximate 4:2 Compressors for Imprecise Multipliers |
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4. |
A Double Error Correction Code for 32-bit Data Words with Efficient Decoding |
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5. |
A Low Power Binary Square Rooter using Reversible Logic |
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6. |
A New Logic for Implementation of Digital Error Correction Block |
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7. |
Fast & Energy Efficient Binary to BCD Converter with Complement Based Logic Design (CBLD) for BCD Multipliers |
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8. |
Design of 32-bit MIPS ALU by Efficient Adders |
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9. |
FPGA Based 64-Bit Low Power RISC
Processor Using Verilog HDL
|
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10. |
Area and Time Efficient Square Architecture |
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11. |
Modified Binary Multiplication Circuit Based On Vedic Mathematics |
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12. |
An Efficient Design Of 16 Bit MAC Unit Using Vedic Mathematics
|
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13. |
16 bit power efficient carry select adder |
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14. |
Dual-quality 4:2 Compressors For Utilizing In Dynamic Accuracy Configurable Multipliers |
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15. |
Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding |
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16. |
Design of Multiplier less Multiple Constant Multiplication for Convolution Circuits |
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17. |
A High-Performance FIR Filter Architecture for
Fixed and Reconfigurable Applications
|
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18. |
Reliable Low-Power Multiplier Design Using
Fixed-Width Replica Redundancy Block
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19. |
A Method to Design Single Error Correction Codes
With Fast Decoding for a Subset of Critical Bits
|
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Back End Design(VHDL/Verilog HDL) |
20. |
Analysis of Adiabatic flip-flops for Ultra Low
Power Applications.
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21. |
Design of Low-Power High-Performance 2–4 and 4–16 Mixed-Logic Line Decoders |
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22. |
Low power area efficient ALU with low power full adder |
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